1. Field
Embodiments of the inventive concept relate to a transistor and semiconductor fuse circuit, a semiconductor device including the transistor and semiconductor fuse circuit, and a semiconductor module including the semiconductor device.
2. Description of Related Art
In general, fabrication of a flash memory device includes sequentially forming a tunnel layer and a charge trap layer on a semiconductor substrate. The flash memory device may include memory cells and fuses. Each of the memory cells may store desired data using a charge trap layer. The charge trap layer may trap or detrap charges through the semiconductor substrate and allow desired electrical data to correspond to each of the memory cells.
In addition, each of the fuses may or may not electrically connect adjacent semiconductor circuits using the charge trap layer. In this case, the charge trap layer may trap or detrap charges through the semiconductor substrate and provide a transistor characteristic to each of the fuses. Thus, the fuses may determine electrical connection or disconnection between adjacent semiconductor circuits using the transistor characteristic.
However, when the fuses electrically operate, charges trapped in the charge trap layer may be leaked through the tunnel layer to the semiconductor substrate. Since the charges are detrapped from the charge trap layer, the fuses cannot embody a desired transistor characteristic using the charge trap layer. Thus, the fuses cannot set the electrical connection between the adjacent semiconductor circuits. As a result, the fuses may deteriorate electrical properties of a flash memory device.
The flash memory device may be disposed in a semiconductor memory module and/or a processor-based system. The semiconductor module and/or the processor-based system may have poor electrical properties due to the fuses of the flash memory device.